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<title>MOVSX/MOVSXD—Move with Sign-Extension </title></head>
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<h1>MOVSX/MOVSXD—Move with Sign-Extension</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>0F BE /<em>r</em></td>
<td>MOVSX <em>r16, r/m8</em></td>
<td>RM</td>
<td>Valid</td>
<td>Valid</td>
<td>Move byte to word with sign-extension.</td></tr>
<tr>
<td>0F BE /<em>r</em></td>
<td>MOVSX <em>r32, r/m8</em></td>
<td>RM</td>
<td>Valid</td>
<td>Valid</td>
<td>Move byte to doubleword with sign-extension.</td></tr>
<tr>
<td>REX + 0F BE /<em>r</em></td>
<td>MOVSX <em>r64, r/m8*</em></td>
<td>RM</td>
<td>Valid</td>
<td>N.E.</td>
<td>Move byte to quadword with sign-extension.</td></tr>
<tr>
<td>0F BF /<em>r</em></td>
<td>MOVSX <em>r32, r/m16</em></td>
<td>RM</td>
<td>Valid</td>
<td>Valid</td>
<td>Move word to doubleword, with sign-extension.</td></tr>
<tr>
<td>REX.W + 0F BF /<em>r</em></td>
<td>MOVSX <em>r64, r/m16</em></td>
<td>RM</td>
<td>Valid</td>
<td>N.E.</td>
<td>Move word to quadword with sign-extension.</td></tr>
<tr>
<td>REX.W** + 63 /<em>r</em></td>
<td>MOVSXD <em>r64, r/m32</em></td>
<td>RM</td>
<td>Valid</td>
<td>N.E.</td>
<td>Move doubleword to quadword with sign-extension.</td></tr></table>
<p><strong>NOTES:</strong></p>
<p>*</p>
<p>In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.</p>
<p>** The use of MOVSXD without REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using MOVSXD without</p>
<p>REX.W.</p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 7-6 in the <em>Intel® 64 and IA-32 Architectures Software Devel-oper’s Manual, Volume 1</em>). The size of the converted value depends on the operand-size attribute.</p>
<p>In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to addi-tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.</p>
<h2>Operation</h2>
<pre>DEST ← SignExtend(SRC);</pre>
<h2>Flags Affected</h2>
<p>None.</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>
<p>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
<p>If the DS, ES, FS, or GS register contains a NULL segment selector.</p></td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2>Virtual-8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#GP(0)</td>
<td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#SS(0)</td>
<td>If a memory address referencing the SS segment is in a non-canonical form.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory address is in a non-canonical form.</td></tr>
<tr>
<td>#PF(fault-code)</td>
<td>If a page fault occurs.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.</td></tr>
<tr>
<td>#UD</td>
<td>If the LOCK prefix is used.</td></tr></table></body></html>